Information
Key Notes
- Journal(s): 18
- Conference(s): 14
- PhD: Current - 5 Awarded - 1
- Event(s) Organized: Conference - 2 FDP - 6
32
PUBLICATIONS6
DOCTORAL STUDENTS5
PROJECTS1
PATENTResearch Areas
Characterization and fabrication of MOS devices/circuits
Compact modeling of novel device for faster circuit analysis
Design of embedded/IoT applications or systems
Novel devices analysis using calibrated TCAD simulations
EDUCATION QUALIFICATION
| Degree | Institute | Year |
|---|---|---|
| Doctor of Philosophy | Indian Institute of Technology Roorkee | 2015 |
| Master of Technology | Indian Institute of Technology Roorkee | 2010 |
| Bachelor of Engineering | MVSR Engineering College, Hyderabad | 2007 |
COURSES HANDLED
| Course | L-T-P | Credit | Degree Level |
|---|---|---|---|
| VLSI Technology(EC2201) | 3-0-0 | 3 | UG |
| Digital Circuit Design(EC201) | 3-0-0 | 3 | UG |
| VLSI Technology(EV203) | 3-0-0 | 3 | UG |
| Digital Circuit Design(EC1205) | 3-0-0 | 3 | UG |
| VLSI Design Verification(EC26034) | 3-0-0 | 3 | PG |
| FPGA based System Design(EC252) | 3-0-0 | 3 | UG |
| Digital System Design(EC1202) | 3-0-0 | 3 | UG |
| Computer Programming(MA1163) | 3-0-2 | 4 | UG |
| CMOS Digital IC Design(EV254) | 3-0-0 | 3 | UG |
| Internet of Things(EC317) | 3-0-0 | 3 | UG |
| Microchip Fabrication Techniques(EC5201) | 3-0-0 | 3 | UG, PG |
| Analog and Digital Electronics(EC181) | 3-0-0 | 3 | UG |
| Advanced Computer Architecture(EC5171) | 3-0-0 | 3 | UG, PG |
| Modern Computer Architecture(EC5271) | 3-0-0 | 3 | PG |
RESEARCH IDs
ORC ID
SCOPUS ID
Google Scholar ID
PUBLICATIONS
Journal(s)
Breaking the Constant-Thickness Assumptions in Ferroelectric Negative Capacitance Transistors,
By Radha Bayya, Nitanshu Chauhan, Satish Maheshwaram, Shuvam Pawar*,
ACS,
Applied Electronic Materials,
vol.8(1),
pp.597-606 ,
2026
Benchmarking NC-CrossFET: Device-Level Insights and System Implications,
By A. S. S. V. Sathvik, R. Bayya, D. Rajesh Reddy, S. Maheshwaram, N. Chauhan and S. Pawar,
IEEE,
Transaction of Electron Devices,
vol.73(4),
pp.2267-2273,
2026
Enhancing Device Performance with Circular Layout Transistors: A Comparative Study of CDGT and CSNT,
By Kallepelli, S., Maheshwaram, S. & P., K,
Springer,
Silicon,
vol.17,
pp.2899–2907,
2025
Enhancing Device Performance with Circular Layout Transistors: A Comparative Study of CDGT and CSNT,
By Sagar Kallepelli, Satish Maheshwaram, P. Kiran Kumar,
Springer Nature,
Silicon,
vol.17,
pp.2899–2907,
2025
Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective,
By Chandana Anguru, Vamsi Krishna Aryasomayajula, Venkata Ramakrishna Kotha, Sresta Valasa, Sunitha Bhukya, Narendar Vadthiya, V Bheemudu, Sagar Kallepelli, Satish Maheshwaram, Praveen Kumar Mudidhe,
IOP Publishing,
ECS Journal of Solid State Science and Technology,
vol.13,
pp.013002,
2024
Design and Performance Analysis of Double Gate Vertically Stacked MoS2 Nanosheet Field Effect Transistor,
By Srikanth Rudravaram, Rajendra Prasad Shukla, Satish Maheshwaram,
IOP Publishing,
Physica Scripta,
vol.,
pp.,
2024
Dielectric Material and Thermal Optimization in Sidewall Spacer Design for Junctionless Nanosheet FETs at Sub-5 nm Technology Node: An Insight into Device and Circuit Performance,
By Vanitha Indhur, Uma Maheshwari Dupati, Manasa Lakkarasu, Sravya Sanga, Sresta Valasa, Venkata Ramakrishna Kotha, Sunitha Bhukya, Narendar Vadthiya, Bheemudu Vadthya, Narendar Malishetty, Satish Maheshwaram,
IOP Publishing,
ECS Journal of Solid State Science and Technology,
vol.13 (10),
pp.103007,
2024
Design and Performance Optimization of Junctionless Bottom Spacer FinFET for Digital/Analog/RF Applications at Sub-5nm Technology Node,
By S Valasa, K. V. Ramakrishna, N Vadthiya, S Bhukya, N. Bheema Rao and S Maheshwaram,
ECS,
J. Solid State Sci. Techol.,
vol.12,
pp.013004,
2023
Benchmarking and Optimization of Circular Double Gate Transistor (CDGT) for Sub 10 nm Nodes,
By K Sagar, S. Maheshwaram,
Springer,
Silicon,
vol.15,
pp.3549,
2023
NDR free negative capacitance CGAAFET at 2nm technology node for low power and high-speed applications,
By Ravi Kothapally, Vadthidya Narendar, Satish Maheshwaram,
Elsevier,
Microelectronics,
vol.142,
pp.106018,
2023
Performance Analysis of Geometric Variations in Circular Double Gate MOSFETs at sub 7 nm Technology Nodes,
By K. Sagar, S. Maheshwaram, V. Narendar,
Elsevier,
Microelectronics Journal,
vol.142,
pp.105986,
2023
A Novel Vertically Stacked Circular Nanosheet FET for High Performance Applications,
By K Sagar, S. Maheshwaram,
ECS,
ECS Journal of Solid State Science and Technology,
vol.11,
pp.063005,
2022
Performance Analysis of Sub 10nm Double Gate Circular MOSFET,
By K Sagar, S. Maheshwaram,
Springer ,
Silicon,
vol.14,
pp.1,
2022
A novel circular double gate SOI MOSFET with raised source/drain,
By K Sagar, S. Maheshwaram,
Semicondcutor Science and Technology,
IOP Semicondcutor Science and Technology,
vol.36 (6),
pp.065009,
2021
Impact of Time Zero Variability and BTI Reliability on SiNW FET-Based Circuits,
By Om Prakash, S. Maheshwaram, Swen Beniwal, Naresh Gupta, N Singh, SK Manhas,
IEEE,
IEEE Transactions on Device and Materials Reliability,
vol.19(4),
pp.741,
2019
Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis,
By S. Maheshwaram, S.K. Manhas, G. Kaushal, B. Anand and N. Singh,
IEEE Transactions on Electron Devices,
IEEE,
vol.60 Issue : 9,
pp.2943,
2013
Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform,
By S. Maheshwaram, S.K. Manhas, G. Kaushal, B. Anand, N. Singh,
IEEE Electron Device Letters,
IEEE,
vol.33 Issue-7,
pp.934,
2012
Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS,
By S. Maheshwaram, S.K. Manhas, G. Kaushal, B. Anand, N. Singh,
IEEE Electron Device Letters,
IEEE,
vol.32 Issue : 8,
pp.1011,
2011
Conference(s)
Band gap engineering via antimony doping in Lead-Free Double Perovskite Cs₂AgBiBr₆ solar cell: A SCAPS-based simulation study
By Valsa Shiva, Pradeep Kumar, Shuvam Pawar and Satish Maheshwaram,
The Advances in Green, Net-Zero Innovation - Sustainability (AGNI-S) conference, organized by the Energy and Environment Department ,
2026
A Thickness-Dependent Analytical Framework for Negative Capacitance Devices
By Radha Bayya, Satish Maheshwaram, Nitanshu Chauhan, and Shuvam Pawar,
Micro and Nanoelectronics Devices, Circuits and Systems: Select Proceedings of MNDCS 2026,
2026
Split Ferroelectric NC Forksheet FETs: A Stability-Oriented Design Approach for Sub-3-nm Nodes
By Bushra Shaik, Radha Bayya, Shuvam Pawar and Satish Maheshwaram,
5th International Conference on Emerging Technology Trends in Electronics, Communication and Networking (ET2ECN-2026),
2026
A Thickness-Dependent Analytical Framework and Variability Investigation for Negative Capacitance Forksheet FETs
By Radha Bayya, Satish Maheshwaram, Nitanshu Chauhan, and Shuvam Pawar,
10th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference,
2026
Improving Breakdown Voltage for AlGaN/AlN/GaN HEMT by Optimizing Edge Passivation Layer
By Madhava Rao Pabathula, Satish Maheshwaram, Shuvam Pawar,
10th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference,
2026
Implementation Of Hybrid Full Adder based 4×4 Braun Multiplier Using UMC 180 nm Technology
By Gargi Agarwal, Shuvam Pawar, Satish Maheshwaram,
Micro and Nanoelectronics Devices, Circuits and Systems: Select Proceedings of MNDCS 2026,
2026
Simulation Study of Vertically Stacked Gate All Around Nanosheet Field Effect Transistor using 2D-MoS2
By Srikanth Rudravaram, Shuvam Pawar, Satish Maheshwaram,
Proceedings of the XXIII International Workshop on Physics of Semiconductor Devices: IWPSD,
2025
Energy Efficient Hardware Accelerator for Traffic Sign Recognition on an Edge Device
By Jahnavi Chandaka, Gopala Krishna Thota, Muralidhar Pullakandam and Satish Maheshwaram,
8th IFIP WG 5.5 International Conference on Internet of Things,
2025
Emerging Two Dimensional Channel Materials for MOSFETs: A Review
By R. Srikanth and S. Maheshwaram,
2022 IEEE International Symposium on Smart Electronic Systems (iSES),
2022
Performance Comparison of Circular Double Gate Transistor (CDGT) With Novel Architectures for High-Performance Applications
By S. Kallepelli and S. Maheshwaram,
2022 IEEE International Symposium on Smart Electronic Systems (iSES),
2022
Impact on the Performance of North Bridge I/O Peripheral Component Interconnect Express Block in Physical Design Flow Considering Two Different Synthesis Corners at Below 10nm Technology Node
By N. Karna, A. J. Rao and S. Maheshwaram,
2022 IEEE International Symposium on Smart Electronic Systems (iSES),
2022
Resistive Calibrated Zero Temperature Coefficient Band Gap Reference (BGR)
By N. Dindhoria, G. S. R. Reddy and S. Maheshwaram,
2022 IEEE International Symposium on Smart Electronic Systems (iSES),
2022
Virtual Mouse Control Using Colored Finger Tips and Hand Gesture Recognition
By VVT Reddy, T Dhyanchand, GV Krishna, and S. Maheshwaram,
2020 IEEE-HYDCON,
2020
Subject Tracking with Camera Movement Using Single Board Computer
By S. Babu, B.S. Pragathi, U. Chinthala, and S. Maheshwaram,
2020 IEEE-HYDCON,
2020
Patent(s)
PROGRAMMABLE ELECTRONIC JACQUARD MACHINE FOR COMPLEX DESIGNS IN HANDLOOM SECTOR (524014)
PROJECT / CONSULTANCY
IC Characterization Facility
Role:
Co-Principal Investigator
Type: Research
Sponsor: DST FIST
Project Cost (INR): 22300000
Date of Commencement: 18-02-2024
Duration: 60 Months
Status: Ongoing
Type: Research
Sponsor: DST FIST
Project Cost (INR): 22300000
Date of Commencement: 18-02-2024
Duration: 60 Months
Status: Ongoing
High Precision Interface Circuit for Capacitive based Sensors (HPICCS) for Defence Applications
Role:
Co-Principal Investigator
Type: Research
Sponsor: MeitY
Project Cost (INR): 9600000
Date of Commencement: 01-11-2023
Duration: 59 Months
Status: Ongoing
Type: Research
Sponsor: MeitY
Project Cost (INR): 9600000
Date of Commencement: 01-11-2023
Duration: 59 Months
Status: Ongoing
Improving Logic Building skills of Adivasi/Schedule Tribe students
Role:
Co-Principal Investigator
Type: Research
Sponsor: Governor's Discretinary Grants, Govt. of Telangana
Project Cost (INR): 1080000
Date of Commencement: 20-03-2023 Date of Completion: 31-03-2024
Duration: 12 Months
Status: Completed
Type: Research
Sponsor: Governor's Discretinary Grants, Govt. of Telangana
Project Cost (INR): 1080000
Date of Commencement: 20-03-2023 Date of Completion: 31-03-2024
Duration: 12 Months
Status: Completed
Radiation Hardened Vertical Nanowire FET Memory Design
Role:
Principal Investigator
Type: Research
Sponsor: RSM project, NIT Warangal
Project Cost (INR): 500000
Date of Commencement: 31-08-2018 Date of Completion: 28-08-2020
Duration: 24 Months
Status: Completed
Type: Research
Sponsor: RSM project, NIT Warangal
Project Cost (INR): 500000
Date of Commencement: 31-08-2018 Date of Completion: 28-08-2020
Duration: 24 Months
Status: Completed
Short Term Training Programme on Machine Learning and Deep Learning for Real time Applications
Role:
Co-Principal Investigator
Type: Research
Sponsor: DST ICPS
Project Cost (INR): 900000
Date of Commencement: 01-03-2019 Date of Completion: 31-03-2020
Duration: 12 Months
Status: Completed
Type: Research
Sponsor: DST ICPS
Project Cost (INR): 900000
Date of Commencement: 01-03-2019 Date of Completion: 31-03-2020
Duration: 12 Months
Status: Completed
RESEARCH FELLOWS / PhD STUDENTS
Current PhD Students
Alavaala R Sekhar Reddy
Area of Research:
Embedded Systems
Chiluka Mani Varshith
Area of Research:
SoC / ASIC design
Pabathula Madhava Rao
Area of Research:
High Electron Mobility Transistor
Ravi Kothapally
Area of Research:
Negative Capacitance Field Effect Transistor
Rudravaram Srikanth
Area of Research:
2D material based MOS device
Previous PhD Students
Kallepelli Sagar
(2023)
Area of Research:
Analysis of Enclosed Circular Double Gate MOSFETs
CONFERENCE / WORKSHOP / SYMPOSIUM / SHORT TERM COURSE / FACULTY DEVELOPMENT PROGRAMME / GIAN
8th IEEE International Symposium on Smart Electronic Systems (iSES)
18-Dec-2022
→
22-Dec-2022
Event Type:
Conference
Role: Finance Chair
Funding Agency: Self‑sponsored
Role: Finance Chair
Funding Agency: Self‑sponsored
8TH IFIP International Internet of Things (IoT) Conference
06-Nov-2025
→
08-Nov-2025
Event Type:
Conference
Role: Editor and Media Chair
Funding Agency: Self‑sponsored
Role: Editor and Media Chair
Funding Agency: Self‑sponsored
System Design Methodologies for Embedded, IoT, AI, & HPC using Intel FPGA
19-Apr-2021
→
30-Apr-2021
Event Type:
Faculty Development Programme
Role: Coordinator
Funding Agency: EICT
Role: Coordinator
Funding Agency: EICT
Content Preparation and Delivery for Online Mode of Teaching (CPDOMT)
05-Oct-2020
→
10-Oct-2020
Event Type:
Faculty Development Programme
Role: Coordinator
Funding Agency: Teaching Learning Centre, NIT Warangal
Role: Coordinator
Funding Agency: Teaching Learning Centre, NIT Warangal
Nanoscale Devices and Circuits
17-Jun-2019
→
22-Jun-2019
Event Type:
Faculty Development Programme
Role: Coordinator
Funding Agency: Electronics and ICT Academy
Role: Coordinator
Funding Agency: Electronics and ICT Academy
Advanced CMOS VLSI
03-Dec-2018
→
08-Dec-2018
Event Type:
Faculty Development Programme
Role: Coordinator
Funding Agency: Electronics and ICT Academy
Role: Coordinator
Funding Agency: Electronics and ICT Academy
FPGA Based Deep Learning Applications in Signal Processing
06-Feb-2023
→
16-Feb-2023
Event Type:
Faculty Development Programme
Role: Coordinator
Funding Agency: Electronics and ICT Academy
Role: Coordinator
Funding Agency: Electronics and ICT Academy
Intricacies of Analog & Mixed Signal design, NKN Winter 2025 courses (GoI initiative for Capacity Building and Skill Development)
17-Feb-2025
→
28-Feb-2025
Event Type:
Faculty Development Programme
Role: Coordinator
Funding Agency: Electronics and ICT Academy
Role: Coordinator
Funding Agency: Electronics and ICT Academy
AWARDS AND ACCOLADES
2025
IEEE Senior Member - April 2025 Onwards
2013
Young Scientist Travel Grant - DST 2013
ADDITIONAL RESPONSIBILITIES
- Faculty Advisor (July, 2024 - June, 2025)
- Facility Coordinator, Design Thinking and Tinkering Lab (June, 2023 - June, 2025)
- Faculty-In-Charge, Network Infrastructure (Data Centre, NKN, LAN and Internet, Software Licenses) (Continuing from May, 2023)
Last updated on April 30, 2026