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Prof. Maheshwaram Satish

PhD (Indian Institute of Technology Roorkee)

Assistant Professor Gr-I

Department of Electronics and Communication Engineering

Room No: EC307   +91-870-2462423
satishm@nitw.ac.in Edit Profile Bio Sketch

Research Areas

 Characterization and fabrication of MOS devices/circuits 

 Compact modeling of novel device for faster circuit analysis 

 Design of embedded/IoT applications or systems 

 Novel devices analysis using calibrated TCAD simulations 

  • Courses Handled
  • Research IDs
  • Selected Publications
  • Project/Consultancy
  • Current PhD Students
  • Awards and Accolades
  • Additional Responsibilities
  • Comprehensive Viva-Voce(EC26093)
  • Digital Circuit Design Lab(EC1211)
  • Summer Internship / Research Experience(EC26091)
  • Digital Circuit Design(EC1205)
  • VLSI Technology(EC2201)
  • Computer Programming(MA1163)
  • Digital Circuit Design(EC201)
  • Digital Circuit Design Lab(EC205)
  • Internet of Things(EC317)
  • CMOS Digital IC Design(EV254)
  • CMOS Digital IC Design Lab (EV257)
  • Microchip Fabrication Techniques(EC5201)
  • Microprocessors(CS201)
  • Programming using Python(EC154)
  • Analog and Digital Electronics(EC181)
  • Python for circuit simulation(EV154)
  • Modern Computer Architecture(EC5271)
  • Advanced Computer Architecture(EC5171)
  • ORC ID: 0000-0002-1760-1545
  • SCOPUS ID: 42161683700
  • Google Scholar ID: l-PZJ8cAAAAJ


  • Design and Performance Analysis of Double Gate Vertically Stacked MoS2 Nanosheet Field Effect Transistor, By Srikanth Rudravaram, Rajendra Prasad Shukla, Satish Maheshwaram, IOP Publishing, Physica Scripta, vol., pp., 2024
  • Dielectric Material and Thermal Optimization in Sidewall Spacer Design for Junctionless Nanosheet FETs at Sub-5 nm Technology Node: An Insight into Device and Circuit Performance, By Vanitha Indhur, Uma Maheshwari Dupati, Manasa Lakkarasu, Sravya Sanga, Sresta Valasa, Venkata Ramakrishna Kotha, Sunitha Bhukya, Narendar Vadthiya, Bheemudu Vadthya, Narendar Malishetty, Satish Maheshwaram, IOP Publishing, ECS Journal of Solid State Science and Technology, vol.13 (10), pp.103007, 2024
  • Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective, By Chandana Anguru, Vamsi Krishna Aryasomayajula, Venkata Ramakrishna Kotha, Sresta Valasa, Sunitha Bhukya, Narendar Vadthiya, V Bheemudu, Sagar Kallepelli, Satish Maheshwaram, Praveen Kumar Mudidhe, IOP Publishing, ECS Journal of Solid State Science and Technology, vol.13, pp.013002, 2024
  • NDR free negative capacitance CGAAFET at 2nm technology node for low power and high-speed applications, By Ravi Kothapally, Vadthidya Narendar, Satish Maheshwaram, Elsevier, Microelectronics, vol.142, pp.106018, 2023
  • Performance Analysis of Geometric Variations in Circular Double Gate MOSFETs at sub 7 nm Technology Nodes, By K. Sagar, S. Maheshwaram, V. Narendar, Elsevier, Microelectronics Journal, vol.142, pp.105986, 2023
  • Design and Performance Optimization of Junctionless Bottom Spacer FinFET for Digital/Analog/RF Applications at Sub-5nm Technology Node, By S Valasa, K. V. Ramakrishna, N Vadthiya, S Bhukya, N. Bheema Rao and S Maheshwaram, ECS, J. Solid State Sci. Techol., vol.12, pp.013004, 2023
  • Benchmarking and Optimization of Circular Double Gate Transistor (CDGT) for Sub 10 nm Nodes, By K Sagar, S. Maheshwaram, Springer, Silicon, vol.15, pp.3549, 2023
  • Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis, By S. Maheshwaram, S.K. Manhas, G. Kaushal, B. Anand and N. Singh, IEEE Transactions on Electron Devices, IEEE, vol.60 Issue : 9, pp.2943, 2013
  • Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform, By S. Maheshwaram, S.K. Manhas, G. Kaushal, B. Anand, N. Singh, IEEE Electron Device Letters, IEEE, vol.33 Issue-7, pp.934, 2012
  • Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS, By S. Maheshwaram, S.K. Manhas, G. Kaushal, B. Anand, N. Singh, IEEE Electron Device Letters, IEEE, vol.32 Issue : 8, pp.1011, 2011

High Precision Interface Circuit for Capacitive based Sensors (HPICCS) for Defence Applications

  • Role Co-Principal Investigator
  • Type Research
  • Sponsor MeitY
  • Duration 59 Months
  • Project Cost (INR) 9600000
  • Status Ongoing

Improving Logic Building skills of Adivasi/Schedule Tribe students

  • Role Co-Principal Investigator
  • Type Research
  • Sponsor Governor's Discretinary Grants, Govt. of Telangana
  • Duration 12 Months
  • Project Cost (INR) 1080000
  • Status Completed

Radiation Hardened Vertical Nanowire FET Memory Design

  • Role Principal Investigator
  • Type Research
  • Sponsor RSM project, NIT Warangal
  • Duration 24 Months
  • Project Cost (INR) 500000
  • Status Completed

Short Term Training Programme on Machine Learning and Deep Learning for Real time Applications

  • Role Co-Principal Investigator
  • Type Research
  • Sponsor DST ICPS
  • Duration 12 Months
  • Project Cost (INR) 900000
  • Status Completed


Alavaala R Sekhar Reddy

  • Area of Research: Embedded Systems

Pabathula Madhava Rao

  • Area of Research: High Electron Mobility Transistor

Ravi Kothapally

  • Area of Research: Negative Capacitance Field Effect Transistor

Rudravaram Srikanth

  • Area of Research: 2D material based MOS device
  • IEEE Senior Member - April 2025 Onwards
  • Young Scientist Travel Grant - DST 2013
  • Faculty Advisor (July, 2024 - June, 2025)
  • Facility Coordinator, Design Thinking and Tinkering Lab (June, 2023 - June, 2025)
  • Faculty-In-Charge, Network Infrastructure (Data Centre, NKN, LAN and Internet, Software Licenses) (Continuing from May, 2023)