NIT Warangal

Information

Room No: ECE 215 +91-870-2462445 sarangam_7@nitw.ac.in Bio Sketch

Key Notes

Journal(s): 8
Conference(s): 8
PhD: Current - 4

16

PUBLICATIONS

4

DOCTORAL STUDENTS

1

PROJECT

1

PATENT

Research Areas

Analog/mixed VLSI circuits

low power VLSI circuits

Sigma-Delta ADCs

VLSI Testing

EDUCATION QUALIFICATION

Degree	Institute	Year
Doctor of Philosophy	National Institute of Technology,Warangal	2023

COURSES HANDLED

Course	L-T-P	Credit	Degree Level
Analog Electronics(EC1261)	3-0-0	3	UG
VLSI Test and Testability(EC26029)	3-0-0	3	PG
Linear IC Applications(EC251)	3-0-0	3	UG
Linear IC Applications(EC1208)	3-0-0	3	UG
Verification Methodologies: UVM(EC16034)	3-0-0	3	PG
Integrated Circuits and Applications(ECM03)	3-0-0	3	UG
VLSI Test & Testability(EC5215)	3-0-0	3	PG
Analog and Digital Electronics(EC181)	3-0-0	3	UG
Low power VLSI Design(EC5253)	3-0-0	3	PG

RESEARCH IDs

PUBLICATIONS

Journal(s)

Design and Implementation of a Secure and Accurate Electronic Voting Machine Using Verilog on Zynq FPGA, By LC Harsha, SD Bharatula, BNK Reddy, K Sarangam, IEEE, Journal of Mobile Multimedia, vol., pp., 2025

Dielectric engineering in 18 nm double gate FinFETs: comparative analysis of high-K materials for enhanced device performance, By K Sarangam, DKC Mirappalli, AS Kumar, CRP Reddy, Springer, Proceedings of the Indian National Science Academy, vol., pp., 2025

Design and Investigation of the 22 nm FinFET Based Dynamic Latched Comparator for Low power Applications, By K Sarangam, Aruru Sai kumar, B Naresh Kuamar Reddy, Springer, Transctions on Electrical and Electronic Materials, vol., pp., 2024

A novel FinFET Based Low Power High Speed Two Stage Dynamic Comparator, By K Sarangam , Bheema Rao Nistala, State science journal , Computer Integrated Manufacturing Systems, vol.28, pp.12, 2023

Design Considerations into Circuit Applications for structurally Optimized FinFET, By K Sarangam, Praveen Kumar Mudidhe, Sresta Valasa, IOP, ECS Journal of Solid State Science and Technology, vol.12, pp., 2023

Design of FinFET Based High gain Low Power Two Stage OTA for Biomedical Applications, By K Sarangam, Bheema Rao Nistala, scope journal, Scope, vol.13, pp., 2023

A Lower Third-order Passive Continues Time Sigma Delta Modulator using FinFET, By K Sarangam , Bheema Rao Nistala, Springer, LNEE, vol.686, pp., 2020

200 kS/s, 10-Bit Low Power SAR ADC for Biomedical Applications, By Lalit Kumar Mandrai, K. Sarangam , MICRO, International Journal of Computer Applications (0975 – 8887) International Conference on Microelectronics, Circuits and Systems (MICRO-2014) , vol., pp., 2014

Conference(s)

Accelerating Sorting Performance on FPGA: Combining Quick Sort and Heap Sort through Hybrid Pipelining, By B. N. Kumar Reddy, K. Sarangam, S. Dandeliya, S. P. Sai Naidu and N. K. P, 2023 IEEE International Symposium on Smart Electronic Systems (iSES), , 2023

An Efficient FSR-based Approach for Self Notifying Chairs to Minimize Long Duration Sitting Postures," By K. Sarangam, T. Appala, B. V. Vani and A. S. Kumar, 2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT),, 2023

Design and Energy Dissipation Analysis of Full-Adder for Low Power Applications Using Reversible Logic Gates By K. Sarangam, B. C. Naik, B. N. Kumar Reddy and A. S. Kumar, 2023 3rd International Conference on Emerging Frontiers in Electrical and Electronic Technologies (ICEFEET), , 2023

An Efficient Predictive Alimentary System using Machine Learning on the edge By B. Seetharamulu, K. Maheedhar, A. Sharma, R. Charan, K. Sarangam and B. N. K. Reddy, 2022 6th International Conference on Devices, Circuits and Systems (ICDCS),, 2022

"A second-order Switched Capacitor Passive Sigma Delta Modulator with Bootstrapped switches in FinFET Technology," By K. Sarangam and N. Bheema Rao, International Conference on Electrical, Communication, and Computer Engineering (ICECCE), 2021

"A FinFET based 2nd-Order Fully Differential Passive Sigma Delta Modulator for Low Power ADC," By K. Sarangam and N. B. Rao, 2020 11th International Conference on Computing, Communication and Networking Technologies (ICCCNT),, 2020

SRAM cell with better read and write stability with Minimum area By B. N. K. Reddy, K. Sarangam, T. Veeraiah and R. Cheruku, TENCON 2019 - 2019 IEEE Region 10 Conference (TENCON),, 2019

A 10-bit 25MSPS low power pipeline ADC for Mobile HDTV Receiver System By K. Dongre, P. Akre, R. Kamdi and K. Sarangam, 2014 International Conference on Electronics and Communication Systems (ICECS),, 2014

Patent(s)

A REAL TIME TRACKING AND STOP REQUEST SYSTEM WITH DYNAMIC AND EMERGENCY ALERTS FOR ELECTRIC VEHICLES (202541016150)

PROJECT / CONSULTANCY

Power management LDO for mobile applications and On-chip temperature sensor for a smart probe for ADA

Role: Co-Principal Investigator
Type: Research
Sponsor: SMDP-C2SD MeitY
Project Cost (INR): 5200088
Date of Commencement: 15-07-2017 Date of Completion: 10-11-2022
Duration: 64 Months
Status: Completed

RESEARCH FELLOWS / PhD STUDENTS