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Prof. P Muralidhar

PhD (National Institute of Technology Warangal)

Associate Professor

Department of Electronics and Communication Engineering

Room No: 203   +91-870-2462442
pmurali@nitw.ac.in Edit Profile Bio Sketch

Research Areas

 Embedded Systems Design ,Digital System Design  

 FPGA based designs ,VLSI Architectures 

 ML and DL Hardware Accelerator Design 

 Video & Image Processing Algorithms and Architectures 

  • Courses Handled
  • Research IDs
  • Selected Publications
  • Project/Consultancy
  • Current PhD Students
  • Awards and Accolades
  • Additional Responsibilities
  • Embedded systems Lab(EC16007)
  • Microcontrollers Lab(EC306)
  • Embedded Hardware Platforms and Programming(EC16001)
  • Advanced Microcontrollers(EC304)
  • Induction Program(IC001)
  • FPGA based design Lab(EC257)
  • Embedded and Real Time Operating Systems(EC354)
  • Hardware Accelerators Design for Machine Learning models(EC16004)
  • Hardware accelerators for machine learning Lab(EC16008)
  • Digital Design and Embedded Systems Lab(EC5106)
  • VLSI Architectures(EC5216)
  • SoC design and Industrial Automation Lab(EC5155)
  • Hardware/Software Co-design(EC5153)
  • Embedded System Design(EC5103)
  • Analog and Digital Electronics Laboratory(EC182)


  • Empowering edge devices: FPGA-based 16-bit fixed-point accelerator with SVD for CNN on 32-bit memory-limited systems, By Yanamala, Rama Muni Reddy, Muralidhar Pullakandam, Wiley, International Journal of Circuit Theory and Applications, vol., pp., 2024
  • High-Speed Power Allocation in NOMA System using FPGA based DNN, By Rama Muni Reddy Yanamala, Muralidhar Pullakandam, World Scientific, Journal of Circuits, Systems and Computers, vol., pp., 2024
  • An Effective Hybrid Deep Learning Model for Single-Channel EEG-Based Subject-Independent Drowsiness Recognition, By Y. Rama Muni Reddy, P. Muralidhar & M. Srinivas, Springer, Brain Topography , vol.37, pp.1-18, 2024
  • A high-speed reusable quantized hardware accelerator design for CNN on constrained edge device, By Rama Muni Reddy Yanamala, Muralidhar Pullakandam , Springer, Design Automation for Embedded Systems, vol.27, pp.165–189, 2023
  • SoC-based Real-Time SVM Classification with Integrated Training Using HLS and PYNQ, By BB Shabarinath, Muralidhar Pullakandam, Elsevier, Microprocessors and Microsystems, vol.101, pp.104878, 2023
  • Object Tracking Based Surgical Incision Region Encoding using Scalable High Efficiency Video Coding for Surgical Telementoring Applications, By Sanagavarapu, Karthik Sairam and Pullakandam, Muralidhar, SPOLECNOST PRO RADIOELEKTRONICKE INZENYRSTVI , CZECH TECHNICAL UNIVERSITY, DEPT OF ELECTROMAGNETIC FIELD, TECHNICKA 2, PRAHA, CZECH REPUBLIC, CZ-16627, Radioengineering, vol.31, pp.2, 2022
  • A motion estimation based algorithm for encoding time reduction in HEVC, By S.Karthik Sai Ram,P.Muralidhar , DEFENCE SCIENTIFIC INFORMATION DOCUMENTATION CENTRE, Defence Science Journal, vol.72, pp.56-66, 2022
  • Low Latency SC Decoder Architecture for Interleaved Polar Codes, By Nandini, Jali, Pullakandam Muralidhar, and Sreehari Rao Patri, SPOLECNOST PRO RADIOELEKTRONICKE INZENYRSTVI , CZECH TECHNICAL UNIVERSITY, DEPT OF ELECTROMAGNETIC FIELD, TECHNICKA 2, PRAHA, CZECH REPUBLIC, CZ-16627, Radioengineering, vol.31, pp., 2022
  • Highly reliable XoR Feed Arbiter Physical Unclonable Function (XFAPUF) in 180 nm process for IoT security, By Raveendra Podeti , Patri Sreehari Rao, P. Muralidhar , Elsevier, Microprocessors and Microsystems, vol.87, pp.104355 , 2021
  • Efficient architecture for global elimination algorithm for H.264 motion estimation, By P Muralidhar, CB Ramarao, Springer, Efficient Architecture for Global Elimination Algorithm for H.264 Motion Estimation, vol.41, pp.47-54, 2016


B.B.Shabarinadh

  • Area of Research: Hardware accelerators for machine learning classifiers

G.RajaSekhar

  • Area of Research: Stocastic computing architectures for signal processing algorithms

Ms.Jujavarapu Sravana

  • Area of Research: Properties of 2D semiconductors for opto-electronic devices

Nagaraju chodavarapu

  • Area of Research: KF(Kalman filter) for object tracking

Nandini Jali

  • Area of Research: VLSI architectures for channel encoding algorithms for wireless communication

R Pavan Kumar

  • Area of Research: Electronic warfare systems

Terkar Anil Narsinhrao

  • Area of Research: Hardware implementation of algorithms: Accelerator for machine learning

T. Gopala Krishna

  • Area of Research: Hardware Accelerator for AI models

Y.Ramamuni Reddy

  • Area of Research: Accelerator architecture design for DNN and machine learning models
  • Vice President SAC(Film & Music Society) (Continuing from July, 2023)
  • ERP Coordinator, Department of Electronics and Communication Engineering (Continuing from April, 2023)
  • Department Purchase Co ordinator (Continuing from January, 2022)
  • EDA Lab and Embedded Systems Lab Incharge (Continuing from July, 2018)