Information
Key Notes
- Journal(s): 20
- Conference(s): 22
- Book Chapter(s): 2
- PhD: Current - 9 Awarded - 5
44
PUBLICATIONS14
DOCTORAL STUDENTS5
PROJECTS1
PATENTResearch Areas
Embedded Systems Design ,Digital System Design
FPGA based designs ,VLSI Architectures
ML and DL Hardware Accelerator Design
Video & Image Processing Algorithms and Architectures
EDUCATION QUALIFICATION
| Degree | Institute | Year |
|---|---|---|
| Doctor of Philosophy | National Institute of Technology Warangal | 2018 |
| Master of Technology | National Institute of Technology Warangal | 2003 |
| Bachelor of Technology | Regional Engineering College Warangal | 1993 |
COURSES HANDLED
| Course | L-T-P | Credit | Degree Level |
|---|---|---|---|
| Embedded Hardware Platforms and Programming(EC16001) | 3-0-0 | 3 | UG, PG |
| Advanced Microcontrollers(EC304) | 3-0-0 | 3 | UG |
| Hardware-Software Co-Design(EC468) | 3-0-0 | 3 | UG |
| Hardware Accelerators Design for Machine Learning models(EC16004) | 3-0-0 | 3 | UG, PG |
| Embedded and Real Time Operating Systems(EC354) | 3-0-0 | 3 | UG |
| VLSI Architectures(EC5216) | 3-0-0 | 3 | UG, PG |
| Hardware/Software Co-design(EC5153) | 3-0-0 | 3 | UG, PG |
| Embedded System Design(EC5103) | 3-0-0 | 3 | UG, PG |
RESEARCH IDs
Google Scholar ID
PUBLICATIONS
Journal(s)
Elevating efficiency: Field-Programmable Gate Array Powered Acceleration of MobileNet V1 with patchwise innovation, double buffering, and Singular Value Decomposition Optimization,
By Rama Muni Reddy Yanamala a, Pullakandam Muralidhar b, Rayappa David Amar Raj
,
Elsevier,
Engineering Applications of Artificial Intelligence,
vol.Volume 163,
pp.Part 3,
2025
Analysis of optical, structural, thermodynamics and electronic properties of silicon tetrafluoride using first-principles analysis under different hydrostatic pressure and composition,
By Sravana, J., P. Muralidhar, and Vundela Padmanabha Red
,
Iop science,
Physica Scripta 100 (6), 065521,
vol.Volume 100, Number 6,
pp.,
2025
Approximate Successive Cancellation Decoder for Polar Codes,
By Nandini, Jali, Muralidhar Pullakandam, and Sreehari Rao Patri.
,
Defence Science Journal,
Defence Science Journal,
vol.Vol 75, Issue 2,
pp.p206,
2025
FPGA-accelerated hybrid CNN-LSTM system for efficient EEG-based drowsiness recognition,
By Rama Muni Reddy Yanamala, Muralidhar Pullakandam,
Springer,
The Journal of Supercomputing,
vol.81,
pp.,
2025
Embedded Hardware-Efficient FPGA Architecture for SVM Learning and Inference,
By Shabarinath, B. B., and Muralidhar Pullakandam
,
IEEE,
IEEE Access,
vol.Volume: 13,
pp.,
2025
A Streaming Dataflow Accelerator for Sparse SVM Kernel Computation in Hyperspectral Image Classification,
By Shabarinath, B. B., and Muralidhar Pullakandam
,
Spolecnost Pro Radioelektronicke Inzenyrstvi , Czech Technical University, Dept Of Electromagnetic Field, Technicka 2, Praha, Czech Republic, Cz-16627,
Radioengineering,
vol.Volume 34, Issue 3,
pp.,
2025
Low Latency Multikernel Polar Codes Using Approximate Processing Element,
By Nandini, Jali, Muralidhar Pullakandam, and Sreehari Rao Patri.
,
Wiley,
International Journal of Circuit Theory and Application ,
vol.Volume53, Issue10,
pp.Pages 5893-5902,
2025
Recursive challenge feed arbiter physical unclonable function (RC-FAPUF) In 180nm process for reliable key generation In IOT security,
By Raveendra Podeti , Patri Sreehari Rao, P. Muralidhar
,
Taylor & Francis,
IETE Technical Review,
vol.VOL. 41,
pp.73-84,
2024
High-Speed Power Allocation in NOMA System using FPGA based DNN,
By Rama Muni Reddy Yanamala,
Muralidhar Pullakandam,
World Scientific,
Journal of Circuits, Systems and Computers,
vol.14,
pp.,
2024
An Effective Hybrid Deep Learning Model for Single-Channel EEG-Based Subject-Independent Drowsiness Recognition,
By Y. Rama Muni Reddy, P. Muralidhar & M. Srinivas,
Springer,
Brain Topography ,
vol.37,
pp.1-18,
2024
Empowering edge devices: FPGA-based 16-bit fixed-point accelerator with SVD for CNN on 32-bit memory-limited systems,
By Yanamala, Rama Muni Reddy,
Muralidhar Pullakandam,
Wiley,
International Journal of Circuit Theory and Applications,
vol.52,
pp.4755 - 4782,
2024
SoC-based Real-Time SVM Classification with Integrated Training Using HLS and PYNQ,
By BB Shabarinath, Muralidhar Pullakandam,
Elsevier,
Microprocessors and Microsystems,
vol.101,
pp.104878,
2023
A high-speed reusable quantized hardware accelerator design for CNN on constrained edge device,
By Rama Muni Reddy Yanamala,
Muralidhar Pullakandam ,
Springer,
Design Automation for Embedded Systems,
vol.27,
pp.165–189,
2023
A Deep Learning Approach in Scalable High Efficiency Video Coding for Fast Coding Unit Size Decision,
By Sanagavarapu Karthik Sairam & Pullakandam Muralidhar
,
Taylor & Francis,
IETE Technical Review,
vol.,
pp.,
2022
Low Latency SC Decoder Architecture for Interleaved Polar Codes,
By Nandini, Jali, Pullakandam Muralidhar, and Sreehari Rao Patri,
Spolecnost Pro Radioelektronicke Inzenyrstvi , Czech Technical University, Dept Of Electromagnetic Field, Technicka 2, Praha, Czech Republic, Cz-16627,
Radioengineering,
vol.31,
pp.,
2022
A motion estimation based algorithm for encoding time reduction in HEVC,
By S.Karthik Sai Ram,P.Muralidhar ,
Defence Scientific Information Documentation Centre,
Defence Science Journal,
vol.72,
pp.56-66,
2022
Object Tracking Based Surgical Incision Region Encoding using Scalable High Efficiency Video Coding for Surgical Telementoring Applications,
By Sanagavarapu, Karthik Sairam and Pullakandam, Muralidhar,
Spolecnost Pro Radioelektronicke Inzenyrstvi , Czech Technical University, Dept Of Electromagnetic Field, Technicka 2, Praha, Czech Republic, Cz-16627,
Radioengineering,
vol.31,
pp.2,
2022
Highly reliable XoR Feed Arbiter Physical Unclonable Function (XFAPUF) in 180 nm process for IoT security,
By Raveendra Podeti , Patri Sreehari Rao, P. Muralidhar ,
Elsevier,
Microprocessors and Microsystems,
vol.87,
pp.104355 ,
2021
High-performance Architecture of Motion Estimation algorithm for video compression,
By P.Muralidhar, C.B.RamaRao
,
World Scientific,
Journal of circuits and systems and computers,
vol.Vol. 25, No. 8,
pp.,
2016
Efficient architecture for global elimination algorithm for H.264 motion estimation,
By P Muralidhar, CB Ramarao,
Springer,
sadhana,
vol.41,
pp.47-54,
2016
Conference(s)
Vision Transformer Implementation on Edge GPU (AGX Orin) for Image Classification
By M Pullakandam, S Soni, S Gupta, RMR Yanamala, GK Thota,
2024 First International Conference on Pioneering Developments in Computer Science & Digital Technologies (IC2SDT),
2024
FPGA(ZCU104) Based Energy Efficient Accelerator for MobileNet-V1
By Ramamuni Reddy Yanamala & Muralidhar Pullakandam, satya Narayana G.N.V. & Jagan Dumpala,
20th IEEE International Colloquium on Signal Processing & Its Applications ,
2024
FPGA Based LSTM Network: A Power and Resource Optimized Solution for Edge Computing
By P Muralidhar, YRM Reddy, PSS Varsha, VS Sharanya, CL Prasanthi,
2024 First International Conference on Electronics, Communication ,
2024
Pneumonia Detection Using Transfer Learning And Hardware Implementation in Edge TPU
By Sujay Kumar Mandal, Muralidhar Pullakandam, Rama Muni Reddy Yanamala,
14th International Conference on Computing Communication and Networking Technologies (ICCCNT),
2023
Pipelined CORDIC Architecture Based DDFS Design and Implementation Authors Sandeep Kumar Verma, Muralidhar Pullakandam, Rama Muni Reddy Yanamala
By Sandeep Kumar Verma, Muralidhar Pullakandam, Rama Muni Reddy Yanamala,
IEEE 20th India Council International Conference (INDICON),
2023
Weapon Object Detection Using Quantized YOLOv8
By M Pullakandam, K Loya, P Salota, RMR Yanamala, PK Javvaji,
2023 5th International Conference on Energy, Power and Environment (ICEPE 2023),
2023
An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device
By Ramamuni Reddy Yanamala and Muralidhar Pullakandam ,
2022 IEEE International Symposium on Smart Electronic Systems (iSES),
2022
The Chaotic-Based Challenge Feed Mechanism for Arbiter Physical Unclonable Functions (APUFs) With Enhanced Reliability in IoT Security
By RaveendraPodeti , Patri Sreehari Rao, P. Muralidhar ,
2022 IEEE International Symposium on Smart Electronic Systems (iSES),
2022
Efficient Successive Cancellation Decoder Architecture for Multi-Kernel Polar Codes
By Nandini,Jali and Muralidhar Pullakandam ,
2022 IEEE International Symposium on Smart Electronic Systems (iSES),
2022
Epileptic Seizure Inference Using Kernelized SVM With Integrated Training on PYNQ Z2”
By B.B.Shabarinath and P.Muralidhar ,
2022 IEEE International Symposium on Smart Electronic Systems (iSES),
2022
An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device
By Rama Muni Reddy Yanamala, Muralidhar Pullakandam,
IEEE International Symposium on Smart Electronic Systems (iSES),
2022
Deep Neural Network Based Next-Frame Prediction in HEVC Video Sequence
By Sanagavarapu Karthik Sairam & Pullakandam Muralidhar ,
2022 IEEE International Symposium on Smart Electronic Systems (iSES),
2022
Custom-IP for Gradient Descent Optimization based on Hardware/Software Co-design Paradigm”
By B.B.Shabarinath,P.Muralidhar ,
2020 24th International Symposium on VLSI Design and Test (VDAT),
2020
Fast encoding in HEVC using subsampling with unsymmetrical octagonal search pattern
By S.Karthik Sai Ram, P.Muralidhar,
2019 IEEE 16th India Council International Conference (INDICON),
2019
Hybrid Fast Motion Estimation for HEVC",
By S.Karthik SaiRam, P.Muralidhar,
6th International Conference on Signal Processing and Integrated Networks (SPIN),
2019
Symmetrical-cross Multi-Hexagon based Exhaustive Search for block motion estimation
By P Muralidhar, A Sravya, PM Rao, CBR Rao,
2015 3rd International Conference on Signal Processing, Communication and Networking (ICSCN),
2015
Customizable Dynamic Hand Gesture recognition System for Motor Impaired people using Siamese neural network
By P Muralidhar, A Saha, P Sateesh,
2015 3rd International Conference on Signal Processing, Communication and Networking (ICSCN),
2015
New fast search block matching Motion Estimation algorithm for H.264 /AVC
By TM Reddy, P Muralidhar, CBR Rao,
2014 International Conference on Devices, Circuits and Communications (ICDCCom),
2014
A High Throughput Diamond Search Architecture with Shift Mechanism for 720p Motion Estimation
By G Srivastava, P Muralidhar, CBR Rao,
2014 International Conference on Devices, Circuits and Communications (ICDCCom),
2014
Efficient Architecture for Variable Block Size Motion Estimation in H.264/AVC
By P.Muralidhar, C.B.Rama Rao, and CYN Dwith,
ACEEE Int. J. on Signal and Image Processing 2014,
2014
Analysis of block matching motion estimation algorithms
By P Muralidhar, CBR Rao,
2013 Fourth International Conference on Computing, Communications and Networking Technologies (ICCCNT),
2013
Architecture design of illumination change progressive motion estimation algorithm
By M Bamankar, P Muralidhar, CB Ramarao,
2013 Fourth International Conference on Computing, Communications and Networking Technologies (ICCCNT),
2013
Book Chapter(s)
Hardware/Software Co-Design for Traffic Sign Inference on Edge Using PYNQ
By B. B. Shabarinath & P. Muralidhar in
Advances in Signal Processing and Communication Engineering,
Springer, Singapore,
Book chapter,
2024
Fast Encoding Using X-Search Pattern and Coded Block Flag Fast Method
By S Karthik Sairam, P Muralidhar in
Advances in Communications, Signal Processing, and VLSI,
Springer,
Book chapter,
2021
Patent(s)
SMART EMBEDDED SYSTEM AND METHOD FOR REAL TIME DETECTION AND NOTIFICATION OF ROAD CONDITIONS (202441080940 A)
PROJECT / CONSULTANCY
Path Rakshak A system for enhancing public transport safety with Real-time ambiance and Driver Monitoring
Role:
Principal Investigator
Type: Research
Sponsor: IIT Mandi iHub & Hci Foundation
Project Cost (INR): 1862000
Date of Commencement: 21-11-2024
Duration: 24 Months
Status: Ongoing
Type: Research
Sponsor: IIT Mandi iHub & Hci Foundation
Project Cost (INR): 1862000
Date of Commencement: 21-11-2024
Duration: 24 Months
Status: Ongoing
HPICCS (High Precision Interfacing Circuit for Capacitive based Sensors for Defence Applications)
Role:
Co-Principal Investigator
Type: Research
Sponsor: Meity, R& Din Electronics group, Chips to Startups, Govt
Project Cost (INR): 9600000
Date of Commencement: 03-05-2018 Date of Completion: 02-05-2023
Duration: 60 Months
Status: Completed
Type: Research
Sponsor: Meity, R& Din Electronics group, Chips to Startups, Govt
Project Cost (INR): 9600000
Date of Commencement: 03-05-2018 Date of Completion: 02-05-2023
Duration: 60 Months
Status: Completed
Advanced CMOS clock recovery circuits for mobile applications P1222
Role:
Co-Principal Investigator
Type: SPARC Project
Sponsor: SPARC, MHRD, Govt of India
Project Cost (INR): 4497466
Date of Commencement: 15-03-2019 Date of Completion: 14-03-2021
Duration: 24 Months
Status: Completed
Type: SPARC Project
Sponsor: SPARC, MHRD, Govt of India
Project Cost (INR): 4497466
Date of Commencement: 15-03-2019 Date of Completion: 14-03-2021
Duration: 24 Months
Status: Completed
Multi-Media and DSP Instruction Set Implementation for 32-bit Processor
Role:
Co-Principal Investigator
Type: Research
Sponsor: DRDO Hyderabad
Project Cost (INR): 990000
Date of Commencement: 10-10-2012 Date of Completion: 09-12-2013
Duration: 14 Months
Status: Completed
Type: Research
Sponsor: DRDO Hyderabad
Project Cost (INR): 990000
Date of Commencement: 10-10-2012 Date of Completion: 09-12-2013
Duration: 14 Months
Status: Completed
Implementation of scalable video codec ME algorithm on FPGA
Role:
Principal Investigator
Type: Research
Sponsor: Minor Research projects from the MHRD Research Seed money Gr
Project Cost (INR): 300000
Date of Commencement: 14-09-2012 Date of Completion: 13-09-2013
Duration: 12 Months
Status: Completed
Type: Research
Sponsor: Minor Research projects from the MHRD Research Seed money Gr
Project Cost (INR): 300000
Date of Commencement: 14-09-2012 Date of Completion: 13-09-2013
Duration: 12 Months
Status: Completed
RESEARCH FELLOWS / PhD STUDENTS
Current PhD Students
G.RajaSekhar
Area of Research:
Stocastic computing architectures for signal processing algorithms
Karthik Venkat sridaran
Area of Research:
VLSI Design Solutions for Articulatory/Verbal disorders
Ms.Jujavarapu Sravana
Area of Research:
Properties of 2D semiconductors for opto-electronic devices
Nagaraju chodavarapu
Area of Research:
KF(Kalman filter) for object tracking
R Pavan Kumar
Area of Research:
Electronic warfare systems
Satyanarayana Maddisani
Area of Research:
VLSI Architectures for DL models
Shiva Sri Charan Chedupaka
Area of Research:
VLSI Architectures for ML
Terkar Anil Narsinhrao
Area of Research:
Hardware implementation of algorithms: Accelerator for machine learning
T. Gopala Krishna
Area of Research:
Hardware Accelerator for AI models
Previous PhD Students
Nandini Jali
(2025)
Area of Research:
VLSI architectures for channel encoding algorithms for wireless communication
B.B.Shabarinadh
(2025)
Area of Research:
Hardware accelerators for machine learning classifiers
Y.Ramamuni Reddy
(2025)
Area of Research:
Accelerator architecture design for DNN and machine learning models
Podeti Raveendra
(2024)
Area of Research:
Exploring Design of Physical Unclonable functions (PUFs) for robust hardware-assisted security
S.Karthik Sai Ram
(2022)
Area of Research:
Video compression algorithms using machine learning approach for encoding time reduction in HEVC
CONFERENCE / WORKSHOP / SYMPOSIUM / SHORT TERM COURSE / FACULTY DEVELOPMENT PROGRAMME
ADDITIONAL RESPONSIBILITIES
- Vice President SAC(Film & Music Society) (July, 2023 - June, 2025)
- ERP Coordinator, Department of Electronics and Communication Engineering (April, 2023 - June, 2025)
- Department Purchase Co ordinator (Continuing from January, 2022)
- EDA Lab and Embedded Systems Lab Incharge (Continuing from July, 2018)
- Faculty Advisor (January, 2018 - June, 2025)
- Time Table Incharge (January, 1995 - June, 2025)
Last updated on December 11, 2025