Information
Key Notes
- Journal(s): 32
- Conference(s): 13
- Book Chapter(s): 3
- PhD: Current - 4 Awarded - 12
48
PUBLICATIONS16
DOCTORAL STUDENTS1
PROJECTResearch Areas
Design and Modelling of On-Chip Inductors for RF Application
Device Modelling and Interconnect Modelling
EDUCATION QUALIFICATION
| Degree | Institute | Year |
|---|---|---|
| Doctor of Philosophy | Indian Institute of Technology, Mumbai | 2008 |
| Master of Technology | College of Engineering, Andhra University, Visakhapatnam | 1991 |
| Bachelor of Engineering | Andhra University College of Engineering Viskhapatnam | 1986 |
COURSES HANDLED
| Course | L-T-P | Credit | Degree Level |
|---|---|---|---|
| Device Modeling(EC26001) | 3-0-0 | 3 | UG, PG |
| VLSI System Design(EC36025) | 3-0-0 | 3 | PG |
| Physical Design Automation(EC26002) | 3-0-0 | 3 | UG, PG |
| Electronic Devices(EV101) | 3-0-0 | 3 | UG |
| Solid State Electronic Devices(EC2104) | 3-0-0 | 3 | UG |
| Device Modelling(EC5202) | 3-0-0 | 3 | PG |
| VLSI System Design(EC5104) | 3-0-0 | 3 | PG |
| Physical Design Automation(EC5251) | 3-0-0 | 3 | PG |
RESEARCH IDs
ORC ID
Google Scholar ID
PUBLICATIONS
Journal(s)
Design and Analysis of Circular Sheet Junctionless Double Gate Vertical Nanotube (CSJL-DG-VNT) FET for DC/Analog/RF Applications: Device to Circuit Implementation,
By Sunitha Bhukya and Bheema Rao Nistala,
IOP SCIENCE,
Physica Scripta,
vol.100,
pp.,
2024
Impact of interface traps and noise analysis on dual material graded channel CGAA FET: A device reliability,
By Praveen Kumar Mudidhe, Bheema Rao Nistala,
Elsevier,
Micro and Nanostructures,
vol.191,
pp.,
2024
Design and Performance Optimization of Junctionless Bottom Spacer FinFET for Digital/Analog/RF Applications at Sub-5nm Technology Node,
By Sresta Valasa, Venkata Ramakrishna Kotha, Narendar Vadthiya, Sunitha Bhukya, Bheema Rao Nistala, Satish Maheshwaram,
IOP SCIENCE,
ECS Journal of Solid State Science and Technology,
vol.12,
pp.,
2023
Circuit Level Analysis of a Dual Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET at Nanoscale Regime,
By Praveen Kumar Mudidhe, Bheema Rao Nistala,
IOP SCIENCE,
ECS Journal of Solid State Science and Technology,
vol.12,
pp.,
2023
Design of FinFET based High gain Low Power Two Stage OTA for Biomedical Applications,
By K Sarangam, Bheema Rao Nistala,
O.P,
Scope,
vol.13,
pp.,
2023
An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation,
By Praveen Kumar Mudidhe, Bheema Rao Nistala,
IOP SCIENCE,
Physica Scripta,
vol.98,
pp.115008,
2023
Temperature analysis of DMGC CGAA FET for future deep space and military applications: an insight into Analog/RF/Self-Heating/Linearity,
By Praveen Kumar Mudidhe, Bheema Rao Nistala,
IOP SCIENCE,
ECS Journal of Solid State Science and Technology,
vol.12,
pp.083005,
2023
Design and Implementation of an ultra-compact high performance prefiltered cascode 5 GHz LNA in 90 nm CMOS using a novel double split on chip IPD inductor for 5G Communications,
By MV Raghunadh, N Bheema Rao,
O.P,
Scope,
vol.13,
pp.,
2023
High performance Double Split Series Stacked Multilayer on chip Inductor for 5G Applications,
By MV Raghunadh, N Bheema Rao,
IJIER,
International Journal for Innovative Engineering Research,
vol.,
pp.,
2023
A Novel Coupled Pyramid Inductor for High Figure of Merit VCO Design for Telemetry Transponder Applications ,
By Murali Banoth, Bheema Rao Nistala ,
Scope,
Scope,
vol.13,
pp.241-250,
2023
Design of a Low Noise Figure Lnausing a Novel Coupled Inductor,
By Murali Banoth, Bheema Rao Nistala ,
Scope ,
Scope,
vol.13,
pp. 1522-1529,
2023
Design optimization of junctionless bottom spacer tapered FinFET: Device to circuit level implementation,
By Sunitha Bhukya, Bheema Rao Nistala,
Elsevier,
Microelectronics Journal,
vol.139,
pp.,
2023
Top of FormBottom of Form Design of a Novel High Q Multi-layer Inductor for VCO Applications,
By B Murali, N Bheema Rao,
Springer,
Silicon,
vol.14,
pp.10115–10121,
2022
Analytical modeling of a dual-material graded-channel cylindrical gate-all-around FET to minimize the short channel effects,
By Praveen Kumar Mudidhe, Bheema Rao Nistala,
Springer,
Journal of computational Electronics,
vol.22,
pp.199-208,
2022
A Novel FinFET-Based Low-Power and High-Speed Two-Stage Dynamic Comparator,
By K Sarangam, Bheema Rao Nistala,
Elsevier,
Computer Integrated Manufacturing Systems,
vol.,
pp.,
2022
Variability analysis of a graded-channel dual-material double-gate strained-silicon MOSFET with fixed charges,
By Subba Rao Suddapalli, Bheema Rao Nistala,
Springer,
Journal of computational Electronics,
vol.21,
pp.243-252,
2022
A Novel Interval Based Protocol for Time Coordination In Wireless Sensor and IOT Networks- An Analytical Analysis,
By Sakuru K.L. Sai Prakash, N. Bheema Rao,
ECTI,
ECTI Transaction on Electrical Engineering, Electronics and Communication,
vol.20,
pp.,
2022
A Novel Loop Based Fine-Gained Network Wide Time Synchronization Over Constrained Delay Paths in Wireless Sensor Network,
By Sakuru K.L. Sai Prakash, N. Bheema Rao,
NINETY NINE PUBLICATION,
Turkish Journal of Computer and Mathematics Education,
vol.,
pp.,
2021
Design of Three Super Compact 5G Bandpass Filters with Integrated Passive Device Technology for 802.11a Wireless LAN,
By MV Raghunadh, N Bheema Rao,
Grenze Scientific Society,
GRENZE International Journal GIJET,
vol.7,
pp.,
2021
K-Hop Iterative Time Syncronization Over a Liner Connected Wireless Sensor Networks,
By Sakuru K.L. Sai Prakash, N. Bheema Rao,
De Gruyter,
Smart Computing Techniques and Applications,
vol.,
pp.,
2021
Analytical modeling of subthreshold current and swing of strained-Si graded channel dual material double gate MOSFET with interface charges and analysis of circuit performance,
By S. Subba Rao, N. Bheema Rao,
Wiley,
International Journal of Numerical Modelling: Electronic Networks,
vol.34,
pp.,
2021
Analog/RF Performance of Triple Material Gate Stack-Graded Channel Double Gate-Junctionless Strained-silicon MOSFET with Fixed Charges,
By Suddapalli Subba Rao, Rani Deepika Balavendran Joseph, Vijaya Durga Chintala, Gopi Krishna Saramekala, D Srikar, Nistala Bheema Rao,
Springer,
Silicon,
vol.14,
pp.7363-7376,
2021
A second order hybrid sigma delta modulator with low gain boosting technique in FINFET technology,
By K Sarangam, Bheema Rao Nistala,
Springer,
Wireless Personal Communications,
vol.,
pp.,
2021
High-quality factor multipath differential fractal inductor for wireless applications,
By Sunil Kumar Tumma, Bheema Rao Nistala,
Emerald,
Circuit World,
vol.48,
pp.333-340,
2021
A Multiresolution Time Domain (MRTD) Method for Crosstalk Noise Modeling of CMOS-Gate-Driven Coupled MWCNT Interconnects,
By S. Rebelli, B. R. Nistala,
IEEE,
IEEE Transactions on Electromagnetic Compatibility,
vol.62,
pp.,
2020
A low power third order passive continueous time sigma delta modulator using FINFET,
By K Sarangam, Bheema Rao Nistala,
Springer,
Electronic Systems and Intelligent Computing,
vol.,
pp.,
2020
High quality factor fractal inductor with complementary split-ring array inclusion,
By Padavala Akhendra Kumar, Narayana Kiran Akondi,
Emerald Publishing,
Circuit World,
vol.,
pp.,
2020
Design of a high performance narrowband low noise amplifier using an on-chip orthogonal series stacked differential fractal inductor for 5G applications,
By Sunil Kumar Tumma, Bheemarao Nistala,
Scientific and Technical research Council of Turkey,
Turkish Journal of Electrical Engineering and Computer Sciences,
vol.,
pp.,
2020
A novel hybrid series stacked differential fractal inductor for MMIC applications,
By Sunil Kumar Tumma, Bheema Rao Nistala,
Emerald,
Circuit World,
vol.46,
pp.137-145,
2019
A Center Potential based Threshold Voltage Model for Graded-Channel Dual-Material Double Gate Strained-Si MOSFET with Interface Charges,
By S. Subba Rao, N. Bheema Rao,
Springer,
Journal of Computational Electronics,
vol.18,
pp.1173-1181,
2019
An Efficient MRTD Model for the Analysis of Crosstalk in CMOS-Driven Coupled Cu Interconnects,
By Shashank Rebelli, N.Bheema Rao,
Czech Technical University,
Radioengineering,
vol.27,
pp.532-540,
2018
Design of an on-chip Hilbert fractal inductor using an improved feed-forward neural network for Si RFICs.,
By P Akhendra Kumar, N.Bheema Rao,
Turkiye Klinikleri Journal of Medical Sciences,
Turkish Journal of Electrical Engineering & Computer Sciences,
vol.26,
pp.2437-2447,
2018
Conference(s)
Design and Optimization of High-Performance On-Chip Fractal Inductors for Wireless Communication Systems
By Chiranjeevi P, Bheema Rao Nistala,
The 7th International Conference on Electronics, Communications and Control Engineering,
2024
A Novel Structure of On-Chip Multilayered Half-Turn Inductor for RF Applications
By B Murali, N Bheema Rao,
2024 IEEE International Conference on Intelligent Signal Processing and Effective Communication Technologies (INSPECT),
2024
Design of a Low Noise Figure LNA using Multilayered Inductor for RF Applications
By B Murali, N Bheema Rao,
2nd International Conference on recent trends in Microelectronics, Automation, Computing and Communications Systems(ICMACC - 24),
2024
High Performance Multilayer Series Coupled Inductor for RF Applications
By B Murali, N Bheema Rao,
4th INTERNATIONAL CONFERENCE ON EMERGING ELECTRONICS AND AUTOMATION (E2A),
2024
A 16Gbps 3rd Order CTLE Design for Serial Links with High Channel Loss in 16nm FinFET
By Pranay Kumar Thota, Siva Kumar Rapina, Bheema Rao Nistala,
2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID),
2023
Optimization of DMGC CGAA FET Under Heavy Ion Irradiation Environment: A Reliability Analysis
By Praveen Kumar Mudidhe, Bheema Rao Nistala,
2023 IEEE 20th India Council International Conference (INDICON),
2023
Performance analysis of Dual Material Graded Channel Cylindrical Gate All Around (DMGC CGAA) FET with Source/Drain Underlap
By Praveen Kumar Mudidhe, Bheema Rao Nistala,
2022 IEEE International Symposium on Smart Electronic Systems (iSES),
2022
Stacked Multi-layer Zig-Zag On-chip Inductor
By Manchala Naveen, N Bheema Rao,
2022 IEEE International Symposium on Smart Electronic Systems (iSES),
2022
Simulation and Performance Analysis of Hetero Dielectric Underlap Asymmetrical Double-Gate MOSFET Using Gate Stack
By Swapna Sarker, Suddapalli Subba Rao, Nistala Bheema Rao,
2021 IEEE 18th India Council International Conference (INDICON),
2021
A Compact Low Loss on-chip-BPF for 5G Radio Front End using IPD Technology
By M. V. Raghunath, Dr. N. Bheema Rao,
2019 Third International conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC),
2020
Design and Performance Analysis of Multilayer On-Chip Band Pass Filter for RF Circuits
By Nagesh Deevi, N Bheema Rao,
2019 IEEE Asia Pacific Conference on Wireless and Mobile (APWiMob),
2020
A High Performance Miniaturized onchip 25 GHz Narrow Bandpass Filter for 5G Radio Access Applications
By M. V. Raghunath, Dr. N. Bheema Rao,
2019 4th International Conference and Workshops on Recent Advances and Innovations in Engineering (ICRAIE),
2020
High Q Half-turn Split Inductor for RF Applications
By B Murali, N Bheema Rao,
2018 5th International Conference on Signal Processing and Integrated Networks (SPIN),
2018
Book Chapter(s)
A Compact IPD Based on-Chip Bandpass Filter for 5G Radio Applications
By M. V. Raghunath and Dr. N. Bheema Rao in
Advances in Communications, Signal Processing, and VLSI,
Springer,
Conference proceedings,
2021
Series stacked non-parallel multipath differential inductor for C band applications
By Sunil Kumar Tumma, Bheema Rao Nistala in
Lecture Notes in Electrical Engineering (LNEE),
Springer,
Lecture Notes Series,
2020
Design and Simulation of a Sub-6 GHz Low Loss Band Pass Filter Using Double Split Inductor for 5G Radio WLAN Applications
By Venkata Raghunadh Machavaram, Bheema Rao Nistala in
Electronic Systems and Intelligent Computing,
Springer,
Proceedings of ESIC 2020,
2020
PROJECT / CONSULTANCY
High Precision Interfacing Circuits for Capacitive based Sensors (HPICCS) for Defence Applications
Role:
Co-Principal Investigator
Type: Research
Sponsor: SMDPC2S, MeiTY
Project Cost (INR): 9600000
Date of Commencement: 01-09-2023
Duration: 60 Months
Status: Ongoing
Type: Research
Sponsor: SMDPC2S, MeiTY
Project Cost (INR): 9600000
Date of Commencement: 01-09-2023
Duration: 60 Months
Status: Ongoing
RESEARCH FELLOWS / PhD STUDENTS
Current PhD Students
Bhukya Sunitha
Area of Research:
Device Modeling
Manchala Naveen
Area of Research:
Spiral Inductors
Pudari Chiranjeevi
Area of Research:
Fractal Inductors
Taduri Sindhupriya
Area of Research:
On-chip Inductors
Previous PhD Students
B Murali
(2024)
Area of Research:
Design and Analysis of Multilayer on-chip Inductors for RF Applications
Praveen Kumar Mudidhe
(2024)
Area of Research:
Modeling and Simulation of Gate and Channel Engineered Cylindrical FET
M V Raghunadh
(2023)
Area of Research:
On-Chip IPD Inductors for 5G Applications
K Sarangam
(2022)
Area of Research:
Design of FinFET Based Low Power ICs for Biomedical
S K L V Saiprakash
(2021)
Area of Research:
Wireless sensors and IOT Networks
Sunil Kumar Tumma
(2020)
Area of Research:
Multilayer Diff. Inductors For RFIC and MMIC Applications
S Subbarao
(2020)
Area of Research:
Modeling and Simulation of DG MOSFET
Rebelli Shashank
(2019)
Area of Research:
On-Chip Interconnects Using MRTD
Padavala Akhendra Kumar
(2017)
Area of Research:
On-chip Fractal Passive Components for Wireless Applications
B V N S M Nagesh Deevi
(2016)
Area of Research:
On chip Multilayer Passive Components for RF Circuits
Korlapati Keerti Kumar
(2016)
Area of Research:
Sub-threshold Leakage Current Reduction in CMOS Circuits
Kavicharan Mummaneni
(2015)
Area of Research:
Crosstalk Estimation Models For VLSI Interconnects
CONFERENCE / WORKSHOP / SYMPOSIUM / SHORT TERM COURSE / FACULTY DEVELOPMENT PROGRAMME / GIAN
ADDITIONAL RESPONSIBILITIES
- Head of the ECE Department (November, 2017 - December, 2019)
- Head Computer center (March, 2013 - February, 2015)
Last updated on January 23, 2025