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All ResearchIDs

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All Publications

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Journal(s)

• Interface Trap Dynamics and Thermal Effects in Novel Junctionless Dual Gate Inverted-U-Shaped FinFETs for Sub-5 nm Node: Device to Circuit Level Implementation, By Bhanu Prakash Bandi, Uday Sankar Srinivas Sornapudi, Sresta Valasa, Venkata Ramakrishna Kotha, Sunitha Bhukya, Praveen Kumar Mudidhe, Shubham Tayal, Narendar Vadthiya, IOP Science, Journal of Physics D: Applied Physics, vol., pp., 2025
• Design and optimization of ferroelectric spacer engineered modified bi-level negative capacitance fet: an analog/rf evaluation perspective, By Santosh Kumar Padhi, Vadthiya Narendar, Atul Kumar Nishad, IEEE, IEEE Transactions on Dielectrics and Electrical Insulation, vol., pp., 2024
• A novel step architecture based negative capacitance (SNC) FET: Design and circuit level analysis, By Santosh Kumar P., Vadthiya Narendar and Atul Kumar Nishad, Elsevier, Microelectronics Journal, vol.146, pp.106139, 2024
• Insights into Substrate Dielectric Engineering of Monolayer MoS2 FET: Digital/Analog/RF perspective to circuit implementation, By Venkata Ramakrishna Kotha, Sresta Valasa, Narendar Vadthiya, IEEE, IEEE Transactions on Dielectrics and Electrical Insulation, vol., pp., 2024
• Interface Trap Characterization in Junctionless Forksheet FET at Sub-3 nm Technology Node: A Reliability Assessment on Digital, Analog/RF, and Circuit Applications, By Gowthami Ryali, Bala Subrahmanyam Pitchuka, Venkata Ramakrishna Kotha, Sresta Valasa, Sunitha Bhukya, Praveen Kumar Mudidhe, Shubham Tayal, Bheemudu Vadthya, Hitesh Borkar, Narendar Vadthiya, IEEE, IEEE Transactions on Device and Materials Reliability, vol., pp., 2024
• Beyond Moore's law–A critical review of advancements in negative capacitance field effect transistors: A revolution in next-generation electronics, By V. Sresta, K. V. Ramakrishna and Vadthiya Narendar , Elsevier, Materials Science in Semiconductor Processing, vol.173, pp.108116, 2024
• Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective, By C Anguru, V K Aryasomayajula, V R Kotha, S Valasa, S Bhukya, V Narendar, V Bheemudu, S Kallepelli, S Maheshwaram and P K Mudidhe , IOP Science, ECS Journal of Solid State Science and Technology, vol.13, No-1, pp. 013002, 2024
• A Proposal for Optimization of Spacer Engineering at Sub-5-nm Technology Node for JL-TreeFET: A Device to Circuit Level Implementation, By R. Andavarapu, Rakesh A., Susmitha B. , Sresta V., V. R. Kotha, Sunitha B., Santosh K. P., and Vadthiya Narendar, IEEE, IEEE Transactions on Electron Devices, vol.71, No-1, pp.453-460, 2024
• Spacer Design Strategies at sub-5 nm technology node for Junctionless Forksheet FET: Bridging Device Optimization and Circuit Efficacy-A Dielectric Perspective, By Devika Gurre, Vinai Dasari, Kavya Mulaga, Sresta Valasa, Venkata Ramakrishna Kotha, Sunitha Bhukya, Praveen Kumar Mudidhe, Shubham Tayal, Bheemudu Vadthya, Narendar Vadthiya, IEEE, IEEE Transactions on Dielectrics and Electrical Insulation, vol., pp., 2024
• Pushing the Boundaries: Design and Simulation Approach of Negative Capacitance Nanosheet FETs with Ferroelectric and Dielectric Spacers at the Sub-3 nm Technology Node for Analog/RF/Mixed Signal Applications, By Sresta Valasa, Venkata Ramakrishna Kotha, Narendar Vadthiya, American Chemical Society, ACS Applied Electronic Materials, vol., pp., 2024
• Design Space Optimization for Eradication of NDR Effect in Dielectric/Ferroelectric Stacked Negative Capacitance Multi-Gate FETs at Sub-3nm Technology for Digital/Analog/RF Applications, By Sresta Valasa, Venkata Ramakrishna Kotha, Shubham Tayal, Narendar Vadthiya, IEEE, IEEE Transactions on Dielectrics and Electrical Insulation, vol., pp., 2024
• Interface traps in the sub-3 nm technology node: A comprehensive analysis and benchmarking of negative capacitance FinFET and nanosheet FETs - A reliability perspective from device to circuit level, By Sresta Valasa, Venkata Ramakrishna Kotha, Narendar Vadthiya, Elsevier, Microelectronics Reliability, vol.160, pp.115479, 2024
• Dielectric Material and Thermal Optimization in Sidewall Spacer Design for Junctionless Nanosheet FETs at Sub-5 nm Technology Node: An Insight into Device and Circuit Performance, By Vanitha Indhur, Uma Maheshwari Dupati, Manasa Lakkarasu, Sravya Sanga, Sresta Valasa, Venkata Ramakrishna Kotha, Sunitha Bhukya, Narendar Vadthiya, Bheemudu Vadthya, Narendar Malishetty, Satish Maheshwaram, IOP Science, ECS Journal of Solid State Science and Technology, vol.13, pp.103007, 2024
• Common Source Amplifier and Ring Oscillator Circuit Performance Optimization Using Multi-Bridge Channel FETs, By V. Bharath Sreenivasulu, N. Aruna Kumari, V. Lokesh, S. K. Vishvakarma and V. Narendar , IOP Science, ECS Journal of Solid State Science and Technology, vol.12, No-2, pp.023013, 2023
• A novel design of coplanar 8-bit ripple carry adder using field-coupled quantum-dot cellular automata nanotechnology, By S. Kassa, N. K. Misra, Seyed S. Ahmadpour, V. Lamba, and Vadthiya Narendar , Springer, European Physical Journal Plus, vol.138, No-731, pp. , 2023
• Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications, By K. V. Ramakrishna, Sresta Valasa, Sunitha Bhukya and Narendar Vadthiya , IOP Science, ECS Journal of Solid State Science and Technology, vol.12, No-9, pp.093007, 2023
• Gate Stack Analysis of Nanosheet FET for Analog and Digital Circuit Applications, By N A. Kumari, V. Vijayvargiya, A. K. Upadhyay, V B. Sreenivasulu, Vadthiya Narendar and P Prithvi , IOP Science, ECS Journal of Solid State Science and Technology, vol.12, No-11, pp.113008, 2023
• Performance Investigation of FinFET Structures: Unleashing Multi-Gate Control through Design and Simulation at the 7 nm Technology Node for Next-Generation Electronic Devices, By S. Valasa, KV Ramakrishna, S. Bhukya, P. Narware, V Bheemudu and Vadthiya Narendar, IOP Science, ECS Journal of Solid State Science and Technology, vol.12, No-11, pp.113012, 2023
• NDR free Negative Capacitance CGAAFET at 2nm Technology Node for Low Power and High-Speed Applications, By R. Kothapally, V. Narendar, S. Maheshwaram, Elsevier, Microelectronics Journal, vol.142, pp.106018, 2023
• Performance analysis of geometric variations in circular double gate MOSFETs at sub-7nm technology nodes, By K. Sagar, S Maheshwaram and V Narendar, ELsevier, Microelectronics Journal, vol.142, pp.105986, 2023
• Design Considerations into Circuit Applications for Structurally Optimised FinFET, By K. Sarangam, S. Valasa1, P. K. Mudidhe, V. Narendar, V. Ramakrishna K., Sunitha B., V. Bheemudu and S. Pothalaiah , IOP Science, ECS Journal of Solid State Science and Technology, vol.12, No-12, pp.123007, 2023
• Design and Performance Optimization of Junctionless Bottom Spacer FinFET for Digital/Analog/RF Applications at Sub-5nm Technology Node, By Sresta Valasa, K. V. Ramakrishna, Narendar Vadthiya, Sunitha Bhukya, N. Bheema Rao and Satish Maheshwaram, IOP Science, ECS Journal of Solid State Science and Technology, vol.12, No-1, pp.013004, 2023
• Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching, By V. Bharath Sreenivasulu and Vadthiya Narendar, Springer, Silicon, vol.14, pp.10401–10411, 2022
• Junctionless gate-all-around nanowire FET with asymmetric spacer for continued scaling, By Bharath Sreenivasulu V. and Vadthiya Narendar, Springer, Silicon, vol.14, pp.7461-7471, 2022
• A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinFET Towards Low-Power and High-Frequency Applications at 5-nm Gate Length, By Bharath Sreenivasulu V. and Vadthiya Narendar, Springer, Silicon, vol.14, Issue - 5, pp.2009-2021, 2022
• Design and Temperature Assessment of Junctionless Nanosheet FET for Nanoscale Applications, By Bharath Sreenivasulu V. and Vadthiya Narendar, Springer, Silicon, vol.14, Issue - , pp.3823–3834, 2022
• Junctionless Gate-All-Around Nanowire FET with Asymmetric Spacer for Continued Scaling, By V. Bharath Sreenivasulu, and Vadthiya Narendar, Springer, Silicon, vol.14, pp.7461–7471, 2022
• Junctionless SOI FinFET with Advanced Spacer Techniques for sub- 3 nm Technology Nodes, By V. Bharath Sreenivasulu and Vadthiya Narendar, Elsevier, AEU-International Journal of Electronics and Communications, vol.145, pp.154069, 2022
• Design insights of nanosheet FET and CMOS circuit applications at 5-nm technology node, By V. Bharath Sreenivasulu and Vadthiya Narendar, IEEE , IEEE Transactions on Electron Devices, vol.69, Issue-8, pp.4115-4122, 2022
• On the design of p-channel step-FinFET at sub-10nm node: A parametric analysis, By Santosh Kumar Padhi, Vadthiya Narendar and Atul Kumar Nishad, Elsevier, Microelectronics Journal, vol.126, pp.105505, 2022
• p-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis, By V. Bharath Sreenivasulu, and Vadthiya Narendar, IOP Science, ECS Journal of Solid State Science and Technology, vol.10, No-12, pp.123001, 2021
• Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes, By Bharath Sreenivasulu V. and Vadthiya Narendar, Elsevier, Microelectronics Journal, vol.116, pp.105214, 2021
• Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length, By Bharath Sreenivasulu V. and Vadthiya Narendar, Elsevier, AEU - International Journal of Electronics and Communications, vol.137, pp.153803, 2021
• Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications, By Bharath Sreenivasulu V. and Vadthiya Narendar, IOP Science , ECS Journal of Solid State Science and Technology, vol.10 Isssue -1, pp.013008, 2021
• Design insights into RF/analog and linearity/distortion of spacer engineered multi-fin SOI FET for terahertz applications, By Bharath Sreenivasulu V. and Vadthiya Narendar, Wiley, International Journal of RF and Microwave Computer-Aided Engineering, vol., pp. e22875, 2021
• A novel bottom-spacer ground-plane (BSGP) FinFET for improved logic and analog/RF performance, By Vadthiya Narendar, Pallavi N., V Bheemudu, B. Sunitha , Elsevier, AEU - International Journal of Electronics and Communications, vol.127, pp.153459, 2020
• Investigation of Short Channel Effects (SCEs) and Analog/RF Figure of Merits (FOMs) of Dual-Material Bottom-Spacer Ground-Plane (DMBSGP) FinFET, By V. Narendar, P. Narware, V. Bheemudu and B. Sunitha, Springer, Silicon, vol.12, Issue -10, pp.2283-2291, 2020
• First Principle Study of Doped Graphene for FET Application, By Vadthiya Narendar, K. Gupta and Shikhar Saxena, Springer, Silicon, vol.11, Issue -1, pp.277–286, 2019
• Performance Enhancement of FinFET Devices with Gate-Stack (GS) High-K Dielectrics for Nanoscale Applications, By Vadthiya Narendar , Springer, Silicon, vol.10, Issue-6, pp.2819-2829, 2018
• Surface potential Modeling of Graded-channel Gate-Stack (GCGS) High-K Dielectric Dual-Material Double-Gate (DMDG) MOSFET and Analog/RF Performance Study, By Vadthiya Narendar, and Kalola Ankit Girdhardas, Springer, Silicon, vol.10, Issue - 6, pp. 2865-2875, 2018
• A Two-Dimensional (2D) Analytical Modeling and Improved Short Channel Performance of Graded-Channel Gate-Stack (GCGS) Dual-Material Double-Gate (DMDG) MOSFET, By Vadthiya Narendar, Shweta Tripathi and R. Bhavani Shankar Naik, Springer , Silicon, vol.10, Issue-6, pp.2399-2407, 2018
• A two-dimensional (2D) analytical surface potential and subthreshold current model for underlap dual-material double-gate (DMDG) FinFET, By Vadthiya Narendar, Saurabh Rai and Siddharth Tiwari, Springer, Journal of Computational Electronics, vol.15, Issue-4, pp.1316 - 1325, 2016
• A two-dimensional (2D) analytical subthreshold swing and transconductance model of underlap dual-material double-gate (DMDG) MOSFET for analog/RF applications, By Vadthiya Narendar, Saurabh Rai, Siddharth Tiwari and R.A. Mishra, Elsevier, Superlattices and Microstructures, vol.100, pp.274-289, 2016
• "Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs), By Vadthiya Narendar and R. A. Mishra, Elsevier, Superlattices and Microstructures, vol.85, pp.357-369, 2015
• A three-dimensional (3D) analytical model for subthreshold characteristics of uniformly doped FinFET, By Shweta Tripathi and Vadthiya Narendar, Elsevier, Superlattices and Microstructures, vol.83, pp.476-487, 2015

Conference(s)

• tudy of HeavyIon Irradiation Effects in FinFETs at Sub-5 nm Technology Node: Reliability Perspective By Sresta Valasa, Venkata Ramakrishna Kotha, Sunitha Bhukya, Vadthya Bheemudu, Shubham Tayal, Narendar Vadthiya, 2024 28th International Symposium on VLSI Design and Test (VDAT), 2024
• A Comparative Analysis of FinFET and Nanosheet FET based Circuits with Geometrical Parameter Variations at sub-5 nm technology node By Vikasvardhan Kothwal, Sresta Valasa, Venkata Ramakrishna Kotha, Sunitha Bhukya, Narendar Vadthiya, Bheemudu Vadthya, 2023 IEEE 20th India Council International Conference (INDICON), 2023
• Proficient n-bit Full Adder Circuit Designs in Field-Coupled QCA Nanotechnology By Sankit Kassa, Neeraj Kumar Misra, Narendar Vadthiya, Vijay Lamba, 2023 IEEE 20th India Council International Conference (INDICON), 2023
• Impact of Dimensional Effects on Subsurface Leakage Current of a Low-VTH Nanoscale MOSFET Under Accumulation Bias By Vadthiya Narendar, Ashutosh Kumar Pandey, Advances in VLSI, Communication, and Signal Processing (VCAS-2018), 2018
• Performance Enhancement of Multi-Gate MOSFETs Using Gate Dielectric Engineering By Vadthiya Narendar, Shrey and Naresh Kumar Reddy, 2018 International Conference on Computing, Power and Communication Technologies (GUCON), 2018
• Short Channel Effects (SCEs) Based Comparative Study of Double-Gate (DG) and Gate-All-Around (GAA) FinFET Structures for Nanoscale Applications By Vadthiya Narendar, Richa Parihar, Ashutosh Kumar Pandey, Advances in VLSI, Communication, and Signal Processing (VCAS-2018), 2018
• Comparative Study of Nanoscale FinFET Structures for High-K Gate Dielectrics By Richa Parihar, Vadthiya Narendar and R A Mishra, 2014 International Conference on Devices, Circuits and Communications (ICDCCom), 2014
• Significance of variation in various parameters on electrical characteristics of FinFET devices By Manish Kumar Rai, Vadthiya Narendar and R A Mishra, 2014 Students Conference on Engineering and Systems, 2014
• High performance Bulk FinFET with bottom spacer By S L Tripathi, Ramanuj Mishra, Vadthiya Narendar and R A Mishra, 2013 IEEE International Conference on Electronics, Computing and Communication Technologies, 2013

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